Chip-Package Interaction and Reliability Impact on Cu/Low-k Interconnects

The exponential growth in device density has yielded high-performance microprocessors containing two billion transistors [1]. The path toward such integration continues to require the implementation of new materials, processes, and design for interconnect and packaging structures. Since 1997, copper (Cu), which has a lower resistivity than aluminum (Al), has been selected as an interconnect material to reduce the RC delay. At the 90 nm technology node, dielectric materials with k (dielectric constant) lower than silicon dioxide (SiO2, k ~ 4) were implemented with Cu interconnects [2, 3]. As the technology advances, the interconnect structure continues to evolve with decreasing dimensions and an increasing number of layers and complexity. At this time, the effort of the semiconductor industry is focused on implementing ultralow-k (ULK) porous dielectric material (k < 2.5) in Cu interconnects to further reduce the RC delay (Figure 2.1) [4]. However, mechanical properties of the dielectric materials deteriorate with increase in the porosity, raising serious concerns about the integration and reliability of Cu/low-k interconnects. For advanced integrated circuits (ICs), the packaging technology is mainly based on the area-array packages, or the flip-chip solder interconnects. This type of first-level structure interconnects the active device side of the silicon (Si) die face